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industrial & multimarket preliminary data sheet revision 1.0, 2011-03-18 ISO1I811T isolated 8 channel digital input with iec61131-2 type 1/2/3 characteristics isoface?
edition 2011-03-18 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
preliminary data sheet 3 v1.0, 2011-03-18 confidential ISO1I811T ISO1I811T confidential revision history: 2011-03-18, v1.0 previous version: targ et data sheet v0.1d8 page subjects (major cha nges since last revision) v1.0 preliminary data sheet
confidential ISO1I811T preliminary data sheet 4 v1.0, 2011-03-18
preliminary data sheet 5 v1.0, 2011-03-xx ISO1I811T 1 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-8 1.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-8 1.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-10 1.2.1 pins of sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-10 1.2.2 pins of serial and parallel logic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-11 2blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p ds-12 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-13 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-13 3.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-13 3.3 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-14 3.4 sensor input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-14 3.5 common error output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-16 3.6 programmable digital input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-16 3.7 parallel interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-17 3.8 serial interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-18 4 standard compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-19 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-21 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-21 5.2 operating conditions and power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p ds-22 5.3 electrical characteristics in put side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-24 5.4 electrical characteristics mi crocontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p ds-26 6 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-3 0
ISO1I811T preliminary data sheet 6 v1.0, 2011-03-xx
preliminary data sheet 7 v1.0, 2011-03-18 ISO1I811T isolated 8 channel digital input with iec61131-2 type 1/2/3 characteristics product highlights ? minimization of power dissipa tion due to constant current characteristic ? status led output for each input ? digital averaging of the input signals to suppress interference pulses ? isolation between input and output using coreless transformer technology c e.g. xe166 i0h i0l gndbb i7h i7l vbb vcc ts /err /cs /rd gnd s e r i a l i z e d e s e r i a l i z e l o g i c ISO1I811T parallel or serial interface digital filter digital filter 8 sensors 2k 12k 330n 2k 12k in0 in7 v fi gndfi ds0 ds1 rosc features ? complete system integration (digital sensor or switch input, galvanic isol ation and intelligent micro- controller or bus-asic interface ? 8-channel input according to iec61131-2 (type 1/2/3) ? integrated galvanic isolation 500vac (en60664-1, ul508) ? 5/3.3v spi and parallel micro-controller interface ? adjustable deglitching filters ? up to 125 khz sampling frequency ? vbb under-voltage detection ? package: tssop 8 x 12.5 mm typical application programmable logic controllers(plc) industrial pc general control equipment description the ISO1I811T is an electrically isolated 8 bit data input interface in tssop-48 package. this part is used to detect the signal states of eight independent input lines according to iec61131-2 type 1/2/3 (e.g. two-wire proximit y switches) with a common ground (gndfi). for operation in accordance with iec61131-2, it is necessary for the device to be wired with resistors rated r v and r ext . (it is recommended to use resistors with an accuracy of 2%, in any case < 5% - mandatory, temperature-coefficients < 200ppm are allowed) an 8 bit parallel/serial c co mpatible interface allows to connect the ic directly to a c system. the input interface supports also a direct control mode and is designed to operate with 3.3/5v cmos compatible levels. the data transfer from input to output side is realized by the integrated coreless transformer technology.
ISO1I811T pin configuration and functionality preliminary data sheet 8 v1.0, 2011-03-18 1 pin configuration and functionality the pin configuration slightly differs for the parallel or the serial interfaces. 1.1 pin configuration the ordering, type and functions of the ic pins are listed in the table 1 . table 1 pin configuration pin parallel interface mo de serial interface mode symbol ctrl 1) type 2) function symbol ctrl. type function 1 gnd a logic ground gnd 2 sel i pd serial parallel mode select sel 3 n.c.. not connected n.c. 4 rosc a clock frequency adjustment rosc 5 vcc a positive 5/3.3v logic supply vcc 6err od, pu error output err 7 gnd a logic ground gnd 8 d0 o ppz data output bit0 sdi i pd spi data input 9 d1 o ppz data output bit1 gnd 10 d2 o ppz data output bit2 gnd 11 d3 o ppz data output bit3 gnd 12 d4 o ppz data output bit4 gnd 13 d5 o ppz data output bit5 sclk i pd spi shift clock input 14 d6 o ppz data output bit6 gnd 15 d7 o ppz data output bit7 sdo o ppz spi data output 16 cs ipuchip select cs 17 rd i pu data read input n.c. not connected 18 gnd a logic ground gnd 19 ds0 i pd filter select input 0 ds0 20 ds1 i pd filter select input 1 ds1 21 gnd a logic ground gnd 22 n.c. not connected n.c. 23 n.c. not connected n.c. 24 gnd a logic ground gnd 25 gndbb a input ground gndbb 26 vbb a positive input supply voltage vbb 27 i0l a input 0 low, led out i0l 28 i0h a input 0 high i0h 29 i1l a input 1 low, led out i1l 30 i1h a input 1 high i1h 31 gndbb a input ground gndbb 32 i2l a input 2 low, led out i2l
preliminary data sheet 9 v1.0, 2011-03-18 ISO1I811T pin configuration and functionality 33 i2h a input 2 high i2h 34 i3l a input 3 low, led out i3l 35 i3h a input 3 high i3h 36 ts a sensor type 1/2/3 select ts 37 gndbb a input ground gndbb 38 n.c. not connected n.c. 39 i4l a input 4 low, led out i4l 40 i4h a input 4 high i4h 41 i5l a input 5 low, led out i5l 42 i5h a input 5 high i5h 33 gndbb a input ground gndbb 44 i6l a input 6 low, led out i6l 45 i6h a input 6 high i6h 46 i7l a input 7 low, led out i7l 47 i7h a input 7 high i7h 48 gndbb a input ground gndbb 1) direction of the pin: i = i nput, o = output, io = input/output 2) type of the pin: a = analog, d = open-drain, pu = internal pull-up resistor, pd = internal pull-down resistor, ppz = push- pull pin with high-impedance functionality table 1 pin configuration pin parallel interface mode serial interface mode symbol ctrl 1) type 2) function symbol ctrl. type function
ISO1I811T pin configuration and functionality preliminary data sheet 10 v1.0, 2011-03-18 figure 1 tssop-48 pinout for parallel and serial interface 1.2 pin functionality the meaning and the functions of the ic pins are described below. 1.2.1 pins of sensor interface vbb (positive supply 9.6-35v sensor supply) vbb supplies the sens or input stage. gndbb (ground for vbb domain) this pin acts as the ground refere nce for the sensor input st age that is supplied by vbb. i0h... i7h (input channel 0 ... 7) sensor inputs with current sink characteristic accordi ng iec61131-2 type 1/2/3 whic h has been selected by pin ts i0l... i7l (led output channel 0 ... 7) this pin provides the output signal to switch on the led if the input voltage and current has been detected as ?high? according the selected type. ts (type select) by connecting a resistor between ts and gndbb the se nsor type (type 1/2/3) can be selected (refer to table 9 for corresponding resistor value). this pin is for static configuration (pin-strapping). the input voltage must not change during operation. gnd sel n.c. rosc /err gnd d0 d1 d3 d4 d5 d6 d7 /cs /rd gnd d2 ds0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 gndbb i6h i6l n.c. i5h i5l i4h gndbb gndbb i3h i7h i7l i2h i3l i2l i4l ts 36 35 34 33 32 31 30 29 28 27 26 25 pinout for parallel interface ds1 vcc gnd n.c. n.c. gnd 19 20 21 22 23 24 i1h i1l i0l i0h vbb gndbb 44 43 42 41 40 39 38 37 48 47 46 45 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 pinout for serial interface 19 20 21 22 23 24 44 43 42 41 40 39 38 37 48 47 46 45 gnd sel n.c. rosc /err gnd sdi gnd gnd gnd sclk gnd sdo /cs n.c. gnd gnd ds0 ds1 vcc gnd n.c. n.c. gnd n .c. = not connected gndbb gndbb i6h i6l n.c. i5h i5l i4h gndbb gndbb i3h i7h i7l i2h i3l i2l i4l ts i1h i1l i0l i0h vbb gndbb gndbb
preliminary data sheet 11 v1.0, 2011-03-18 ISO1I811T pin configuration and functionality 1.2.2 pins of serial and parallel logic interface some pins are common for both interface types, some ot hers are specific for the parallel or serial access. vcc (positive 3.3 / 5v logic supply) vcc supplies the output interface that is electrically isol ated from the sensor input stage. the interface can be supplied with 3.3 / 5v. gnd (ground for vcc domain) this pin acts as the ground reference for the uc-interface that is supplied by vcc. rosc (clock adjustment) a high precision resistor has to be connected between rosc and gnd to guarantee the frequency accuracy of the sampling clock. err (error output) the low active err signal contains the or-wired information of the sensor input missing voltage (mv) detection and the internal data transmission failure detection unit. the output pin err provides an open drain functionality. a current source is also connected to the pin err . in normal operation the signal err is high. see section 3.5 for more details. ds0, ds1 (filter select) when pulling those pins to vcc or to gnd, the internal filter delay can be selected (see table 10 ). these pins are for static configuration (pin-strapping). th e input voltage must not change during operation. cs (chip select) when this pin is in a logic low state, the ic interface is enabled and data can be transferred. sel (serial or para llel mode select) when this pin is in a logic high state, the ic operates in serial mode. fo r parallel mode operation the pin has to be pulled in logic low state. this pin has an internal pull-down resistor. the following pins are provided by the parallel interface d7:d0 (data output bit7 ... bit0) the pins d0 .. d7 are the outputs for data read. rd (read select ) by pulling this pin down, a read tr ansaction is initiated on the dat a bus and the data becomes valid. the following pins are provided by the serial interface sclk (serial interface shift clock) output data is updated with the falling edge of this input clock signal. sdi (serial interface input data) sdi is put into a fifo dedicated to the sensor data bits (no internal registers write operation supported, only daisy chain). input data is sampled with the rising edge of sclk. sdo (serial interface data) sdo provides the sensor data bits.
ISO1I811T blockdiagram preliminary data sheet 12 v1.0, 2011-03-18 2blockdiagram figure 2 block diagram i1 h i1l i2 h i2l i3 h i3l i4 h i4l i5 h i5l i6 h i6l i7 h i7l sensor circuit 0 i0 h i0l gndbb data data data data data data data data s e r i a l i z e mv d e s e r i a l i z e u p d a t e g a t e /err interface handler /cs /rd sdi d7 d6 d5 d4 d3 d2 d1 d0 sclk sdo parallel interface serial interface gnd uvlo vcc vali- dation uvlo vbb tx/rx control ts type selector sensor circuit 1 sensor circuit 2 sensor circuit 3 sensor circuit 4 sensor circuit 5 sensor circuit 6 sensor circuit 7 ds0 tx/rx control data data data data data data data data filter 7 filter 6 filter 5 filter 4 filter 3 filter 2 filter 1 filter 0 startup common error osc clk rosc ds1 sel
preliminary data sheet 13 v1.0, 2011-03-18 ISO1I811T functional description 3 functional description the ISO1I811T is an electrically isolated 8 bit data input in terface. this part is used to detect the signal states of eight independent input lines according to iec61131-2 type 1/2/3 (e.g. two-wire proximity switches) with a common ground (gndbb). 3.1 introduction the current in the input circuit is determined by the switch ing element in state ?0? and by characteristics of the input stage in state ?1?. the octal input device is intended for a configuration comp rising two specified external resistors per channel, as shown in the block diagram. as a result the powe r dissipation within the package is at a minimum. the voltage dependent current th rough the external resistor r ext is compensated by a negative differential resistance of the current sink across pins ixh and ixl, therefore input inx behaves like a constant current sink. the comparator assigns level 1 or 0 to the voltage presen t at input i. to improve interference protection, the comparator is provided with hysteresis. a status le d is connected in series with the input circuit (r ext and current sink). if no led is used an external resistor of 2 k ? should be connected between ixl and gndbb. the specified switching thresholds may chan ge if the resistor is used. the led drive short-circuits the status led if the comparat or detects ?0?. a constant current sink in parallel with the led reduces the operating current of the led, and a voltage limiter ensures that the input circuit remains operational if the led is interrupted. the specified swit ching thresholds may change if the led is interrupted. for each channel an adjustable digital filter is provided which samples the comparator signal at a rate selected by the pins ds0 and ds1. the digital filter is designed to provide averaging characteristics. if the input value remains the same for the selected number of sampling values than, the output changes to the corresponding state. the control interface is compatible to standard microcontrollers. furthermore a direct control mode can be selected that allows the direct control of the outputs d0...d7 by means of the inputs i0h...i7h without any additional logic signal. the c compatible interfaces allow a direct connection to the ports of a microcontroller without the need for other components. the diagnostic logic on the chip monitors the internal data transfer as well as the sensor input supply. the information is send via the internal core less transformer to the pin err at the input interface 3.2 power supply the ic contains 2 electrically isolat ed voltage domains that are independent from each other. the microcontroller interface is supplied via pin vcc and the input stage is supplied via pin vbb. the di fferent voltage domains can be switched on at different time. figure 3 shows the start up behaviour if both voltage domains are powered by an external power supply. if the vcc and vbb voltage have reached their operating r ange and the in ternal data transmission have been star ted successfully, the ic indicates the end of the start up procedur e by setting the pin err to logic high.
ISO1I811T functional description preliminary data sheet 14 v1.0, 2011-03-18 figure 3 start-up 3.3 internal oscillator an external resistor has to be connected to rosc pin and allows the adjustment of the frequency as shown in figure 4 . figure 4 internal frequency setting at rosc the internal oscillator provides the sc an clock for the sampling of the sensor data as well as the internal digital averaging filters. therefore the filter times as defined in the table 10 for the typical freq uency of 125 khz will change accordingly. as an example, it is possible to de fine filter time longer than 20 ms by reducing the internal oscillator frequency. 3.4 sensor input the sensor input structure is shown in figure 5 . due to its active current a v-i-characteristic as shown in figure 6 is maintained. this v-i-curve is well within the iec 61131 standard require ments of type 1 and type 3 sensors, respectively. type 2 sensors are suppor ted as well with the restriction that 2 input channels have to be used in parallel i.e. only only 4 channels are available. it is recommended to choose for the external resistors rext, rv, rled an accuracy of 2 % (< 5% is mandatory) otherwise the v/i-char acteristic shown in figure 6 cannot be guaranteed. tds_ startup _ timing_std. vsd v b b vbb uvlo /err vbb missing voltage v c c vcc uvlo 1 0 t errstart 0 20 40 60 80 100 120 140 160 50 70 90 110 130 150 170 190 210 230 resistance at rosc (kohm) khz
preliminary data sheet 15 v1.0, 2011-03-18 ISO1I811T functional description figure 5 sensor input figure 6 sensor input characteristics 12k (8.5k *) 2k (1,5k *) inx ixh ixl datax v fi vbb gndbb sensor x x = 1,...,8 *) : for type2 r ts ts -3v 5v 15v/11v 0. 5ma 2ma/3ma 15ma v inxdset v inxdclr i inxsnkc,m v fi =30v data bit must be zero data bit must be one active current sink v inxdhys
ISO1I811T functional description preliminary data sheet 16 v1.0, 2011-03-18 3.5 common error output the input (vbb) missing voltage status which is transmitted via the int egrated coreless transformer to the output block and the internal data transmission monitoring inform ation are evaluated in the common error output block, see figure 7 . in case of an internal data transmission error the data bits are replaced by the last valid transmission. moreover, if four consecutive erroneous data transmissions (te1=1, see figure 7 ) occur, an internal error signal te4 (see figure 7 ) is set. the average filters are re set. this status is held until four consecutive error-free transmissions (te1=0) occur. an example timing diagram is shown in figure 7 . the internal w4s (wait for sense) signal indicates whether the sense input interface is operating properly or not. this internal error signal is or-wir ed with the current vbb missi ng voltage status. since the output erro r signal is low-active, the or-wired result is negated. the output stage at pin err has an open drain functionality with a pull-up resistor. see table 12 for the electrical characteristics. figure 7 common error output 3.6 programmable digital input filter the sensor data bits can be filtered by a configurable digital input filter. if selected, the filter changes its output according to an averaging rule with a selectable aver age length. when the sensor state changes without any spikes and noise the change is delayed by the averaging length. sensor spikes that are shorter than the averaging length are suppressed. figure 8 shows the behavior of the filter. figure 8 digital filter behavior the averaging length is selected using the configuration pins ds0 and ds1. see table 10 for the different setting options including filter bypass. the filters are dimensioned for the nominal internal sampling f scannom . the corresponding filter delays can be adjus ted by changing the oscillato r frequency i.e. by tuni ng the resistor at the rosc pin. filter n o r scan trigger transmission error mv trig te 1 te1 te4 vbb missing voltage trig te 4 0123 0123 /err w4s wait for sense scan trigger filter input filter output filter state output is 1 output is 0 output is unchanged 0 1 2 n-1 n-2 averaging time n-3
preliminary data sheet 17 v1.0, 2011-03-18 ISO1I811T functional description 3.7 parallel interface mode the ISO1I811T contains a parallel interface that can be se lected by pulling the sel pin to logic low state. it can be directly controlled by the microcontroller output ports. ( figure 9 , left side). the output pins d7:d0 are in state ?z? as long as cs =1. otherwise, new sensor data bits bi ts are sampled with the falling edge of rd and provided at pins d7:d0. the parallel interface can also be switched over to a direct control mode to observe continously the changes of the inputs i0h ... i7h by means of the corresponding ou tputs d7:d0 without additional logic signals. to activate the parallel direct control mode pin cs and pin rd have to be connected both to ground (permanently as in figure 9 , right side or by the microcontroller ports). th e direct control mode is entered when at least cs and rd are held low for t direct ( table 14 ). figure 9 parallel bus configuration for c-control -mode (left) or direct control mode (right) the timing requirements for the parallel interface are shown in figure 10 and in table 14 . figure 10 parallel bus timing vcc /cs /rd d0 d1 d2 d3 d4 d5 d6 d7 ISO1I811T mcu (e.g. xe166) or asic vcc /cs /rd d0 d1 d2 d3 d4 d5 d6 d7 ISO1I811T mcu (e.g. xe166) or asic parallel _ interface 1 .vsd vcc vcc sel sel /cs t css /rd d7:d0 data t rd data direct control mode t dir ect t valid t csd ~3 scan cycles t valid data data data t scan scan event t scan t rdlow t float
ISO1I811T functional description preliminary data sheet 18 v1.0, 2011-03-18 3.8 serial interface mode the ISO1I811T contains a seri al interface that can be acti vated by pulling the sel pin to logic high state. it can be directly controlled by the microcontroller output port s. the output pin sdo is in state ?z? as long as cs =1. otherwise, the bits are samp led with the falling edge of cs . with every falling edge of sclk the bits are provided serially to the pin sdo, respectively. at the same time, the input to sdi is put into an 8bit fifo buffer sampled with the rising edge of sclk. when all 8 internally sampled bits from sdi input have been put to sdo, the buffered bits are provided to these pins (daisy chain mode). the timing requirements for the parallel interface are shown in figure 11 and in table 15 . figure 11 serial bus timing several spi topologies are supported: pure bus topology and daisy-chain ( figure 12 ). of course independent individual control with dedicated spi controller interfaces for each slave ic are possible, as well. figure 12 example spi topologies transmit edge receive edge t sclk_valid msb t su t hd /cs sclk sdi sdo lsb t su t csh msb lsb t csd t float t cs_valid inactive active t sclk t sclk_su sclk /cs sdo a sclk /cs sdo b sclk /cs sdo c sclk /cs sdo d sclk /cs sdo sdi a sclk /cs sdo sdi b sclk /cs sdo sdi c sclk /cs sdo sdi d mcu or asic sclk miso mcu or asic sclk miso spi_ topologies .vsd
preliminary data sheet 19 v1.0, 2011-03-18 ISO1I811T standard compliance 4 standard compliance the ISO1I811T allows the design of a sensor interface compliant with the standard requirements listed below: system insulation characteristics as shown in table 3 , system maximum ratings as shown in table 2 . there requirements are valid for an application using the ISO1I811T including external circuitry (as proposed in figure 13 ), not for the ic alone. note: when the ic is not supplie d, probing of the digital input interface is still possible du e to the external circuitry, i.e. the 12k resistor and the led. in addition to the current through the led a small current i ixh flows through the pins ixh and ixl. figure 13 recommended application circuit figure 14 system insulation characteristics table 2 system absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. field input voltage overvoltage 1300 ms v fiov -45 +45 v input voltage inx v inx -45 +45 v c e.g. xe166 i0h i0l gndbb i7h i7l vbb vcc ts /err /cs /rd gnd s e r i a l i z e d e s e r i a l i z e l o g i c ISO1I811T parallel or serial interface digital filter digital filter 8 sensors 2k 12k 330n 2k 12k in0 in7 v fi gndfi ds0 ds1 rosc +? io v iso r io ,c io
ISO1I811T standard compliance preliminary data sheet 20 v1.0, 2011-03-18 table 3 system insulation characteristics parameter symbol values unit note / test condition min. typ. max. climatic classification tbd c/c/ days pollution degree (din vde 0110/1.89, din en 60664-1) 2 minimum external clearance clr 6.7 mm minimum external creepage cpg 6.2 mm comparative tracking index cti 550 v maximum working insulation voltage v iso 500 v ac 1min duration 1) 1) not subject to production test, verified by characterization approval ul1577 pending approval csa pending approval en61131-2 pending
preliminary data sheet 21 v1.0, 2011-03-18 ISO1I811T electrical characteristics 5 electrical characteristics this section comprises: ? operating conditions and power supply (see section 5.2 ) ? electrical characteristics input side (see section 5.3 ) ? electrical characteristics microcontroller interface (see section 5.4 ) tolerance values always contain the sum of process-rela ted tolerance values and tolerance-values based on the temperature drift within the specified temperature range. 5.1 absolute maximum ratings all voltages at pins 25 to 48 are measured with respect to ground gndbb. all voltages at pins 1 to 24 are measured with respect to gnd. the vo ltage levels are valid if other ratings are not violated. the two voltage domains vcc, gnd and vbb, gndbb are internally electrically isolated. stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating only for functional op eration of the device at these or any other conditions above those indicated in the operational sections of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4 absolute maximum ratings parameter symbol value unit note / test condition min. max. continuous voltage at pin vbb v vbb -0.3 45 v power dissipation must not exceed max-value peak voltage vbb, overvoltage 500 ms v vbb -0.3 45 v supply voltage vcc v vcc -0.3 6.5 v continuous voltage at logic pins 1 - 24 (except vcc and gnd pins) v log -0.3 6.5 v continuous voltage at pin ts -0.3 6.5 v junction temperature t j -40 150 c storage temperature t s -50 150 c power dissipation p tot 800 mw input voltage range v ixh -45 45 v input voltage range v ixl -0.3 5 v error pin sink current (err =0) i errsink 5mav err < 0.25v vcc electrostatic discharge voltage (human body model) according to jesd22-a114-b v esd ??2.5kv electrostatic discharge voltage (charge device model) according to esd stm5.3.1 - 1999 v esd ??1.5kv
ISO1I811T electrical characteristics preliminary data sheet 22 v1.0, 2011-03-18 5.2 operating conditions and power supply for proper operation of the device, absolute maximum rating ( section 4 ) and the parameter ranges in table 5 must not be violated. exceeding the limits of operating condition parameters may result in device malfunction or spec violations. the power su pply pins vbb and vcc have t he characteristics given in table 7 . table 5 operating range parameter at t j = -40 ... 125c symbol value unit note / test condition min. max. supply voltage logic vcc v vcc 2.85 5.5 v related to gnd supply voltage senses vbb v vbb 9.6 35 v related to gndbb ambient temperature t a -40 85 v junction temperature t j -40 125 c common mode transient dv iso /dt -25 25 kv/ s magnetic field immunity |h im | 30 a/m iec61000-4-8 table 6 thermal characteristics parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol limit values unit note / test condition min. max. thermal resistance junction - case top r thjc_top 15.0. k/w measured on top side) 1) 1) not subject to production test, specified by design thermal resistance junction - case bottom r thjc_bot 13.8. k/w ) 1) thermal resistance junction - pin r thjp 11.8 k/w ) 1) thermal resistance @ 2 cm2 cooling area 2) (thermal conductance only by radiation and free convection) 2) device on 50 mm x 50 mm x 1.5 mm epo xy pcb fr4 with 2 cm2 (one layer, 35 m thick) copper area. pcb is vertical without blow air. r th(ja) 88.6 k/w ) 1) table 7 electrical characteristics of the power supply pins parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. vbb uvlo startup threshold v vbbon 9.6 v vbb uvlo shutdown threshold v vbboff 8.0 v vbb uvlo hysteresis v vbbhys 1v vbb missing voltage off (mv) threshold v vbbmvoff 13.9 v vbb missing voltage on (mv) threshold v vbbmvon 12.1 v glitch filters for vbb missing voltage and undervoltage t vbbfil 40 s ) 1) undervoltage current for vbb i vbbuv 3.5 ma v vbb < v vbbon
preliminary data sheet 23 v1.0, 2011-03-18 ISO1I811T electrical characteristics quiescent current vbb i vbbq 5mav vbb = 24 v, i inx = 0, vcc = 0v undervoltage current for vbb i vbbuv 3.5 ma v vbb < v vbbon startup delay (time between vbbon/vccon and err high) t errstart 130 s digital filter bypassed ) 1) startup delay (time between vbbon/vccon and first data output) t vxxon 130 s digital filter bypassed) 1) vcc uvlo startup threshold v vccon 2.85 v vcc uvlo shutdown threshold 2) v vccoff 2.5 v vcc uvlo threshold hysteresis v vcchys 0.1 v quiescent current vcc i vccq 5.5 ma v vcc = 5 v, v vbb = 0v) 1) quiescent current vcc i vccq 3.0 ma v vcc = 3.3 v, v vbb = 0v) 1) 1) valid for f scantyp = 100khz 2) note that the specified operation of the ic requires v vcc as given in table 5 table 7 electrical characteristics of the power supply pins (cont?d) parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max.
ISO1I811T electrical characteristics preliminary data sheet 24 v1.0, 2011-03-18 5.3 electrical charact eristics input side the electrical characteristics of the input side (pins 1-24) are given in table 8 . note that some parameters refer to in0 to in7 which are nodes of external circuitry (see figure 5 or figure 13 ). electrical characteristics with respect to these nodes are given for the system including the external ci rcuitry and not for the ic alone. see also figure 6 for the different threshold parameters. table 8 sensors inputs parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. sink current limit at saturation edge type 1/3 i inxsnkc13 2.3 ma v vbb =v vbbon , v inx =6.7v, v ixl = 1.2v sink current limit at saturation edge type 2 i inxsnkc2 3.3 ma v vbb =v vbbon , v inx =6.7v, v ixl = 1.2v sink current limit at maximum input voltage type 1/3 i inxsnkm13 3.4 ma v vbb =35v, v inx =30v, v ixl = 2.5v sink current limit at maximum input voltage type 2 i inxsnkm2 4.8 ma v vbb =35v, v inx =30v, v ixl = 2.5v led supply current at maximum input voltage, type 1/3 i ixlmax 2.1 3.1 ma v vbb =35v, v inx =30v, v ixl = 2.5v led supply current at maximum input voltage, type 2 i ixlmax 3.1 4.5 ma v vbb =35v, v inx =30v, v ixl = 2.5v led supply current at high threshold type 3 i ixl1 1.5 2.5 ma v vbb =v vbbon , v inx =11v, v ixl = 2.5v led supply current at high threshold type 2 i ixl2 2.3 3.6 ma v vbb =v vbbon , v inx =11v, v ixl = 2.5v led supply current at high threshold type 1 i ixl3 1.6 2.6 ma v vbb =v vbbon , v inx =15v, v ixl = 2.5v led voltage v fled 1.9 3.0 v ) 1) sense voltage switching threshold, l h (type 1) v inxdset(1) 15 v vbb =24v v ixl = 2.5v) 2) sense voltage switching threshold h l (type 1) v inxdclr(1) 11 v vbb =24v v ixl = 2.5v) 2) hysteresis h ? l (type 1) v inxdhys(1) 1 sense voltage switching threshold l h (type 2) v inxdset(2) 11 v vbb =24v v ixl = 2.5v) 2) sense voltage switching threshold h l (type 2) v inxdclr(2) 7v vbb =24v v ixl = 2.5v) 2) hysteresis h ? l (type 2) v inxdhys(2) 0.65 sense voltage switching threshold l h (type 3) v inxdset(3) 11 v vbb =24v v ixl = 2.5v) 2) sense voltage switching threshold h l (type 3) v inxdclr(3) 7v vbb =24v v ixl = 2.5v) 2)
preliminary data sheet 25 v1.0, 2011-03-18 ISO1I811T electrical characteristics hysteresis h ? l (type 3) v inxdhys(3) 0.7 input sink current when v vbb =0 i ixhq 300 a v vbb =0v v ixh =30v, ixl = open 1) not subject to production test, specified by design 2) clamped to 2.5v if ?logic 1?, internally limited if logic ?0? table 9 setting at the configuration pin ts parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. ts pull-down resistance for type 1 selection r tspd1 33 ? ) 1) 1) required for operation ts pull-down resistance for type 2 selection r tspd2 33 k ? 2)1) 2) only 4 channels can be used for this case. ts pull-down resistance for type 3 selection r tspd3 330 k ? ) 1) max. ts pin load capacitance c tsmax 20 pf ) 1) table 8 sensors inputs (cont?d) parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max.
ISO1I811T electrical characteristics preliminary data sheet 26 v1.0, 2011-03-18 5.4 electrical characteristics microcontroller interface timing characteristics refer to c l < 50 pf and r l >10k ? . table 10 sensor scanning and averaging parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. scan frequency range f scanrge 50 150 khz ) 1) refer to figure 4 1) not subject to production test, specified by design input scan propagation delay t ctdelay 40 s applies equally to all channels) 2) filter bypass delay t bypass 10 s ) 2) 2) valid for f scantyp = 100khz input scan jitter ? t scan tbd s ) 2) input scan processing delay t delay 60 s ) 2) digital filter monitoring time n=125 d t filt01 1.0 ms ds0=l, ds1=h) 2) digital filter monitoring time n=400 d t filt02 3.2 ms ds0=h, ds1=l) 2) digital filter monitoring time n=1248 d t filt03 10.0 ms ds0=l, ds1=l) 2) digital filter monitoring time filter is bypassed t filtoff 10 s ds0=h, ds1=h) 2) table 11 setting at the config uration pin (cl kadj) see also figure 4 parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. rosc resistance to gnd r osc 73.2 221 k ? e96 resistor rosc pin regulated voltage v roscreg 1.2 v max. roscpin load capacitance c roscmax 5pf) 1) 1) required for operation table 12 error pin (err ) parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. error pin pull-up resistance (err =1) r errpu 50 k ? maximum switching frequency (err f sw 10 125 khz ) 1) error pin low voltage v errol 0.25v vcc vi fiol = 5ma
preliminary data sheet 27 v1.0, 2011-03-18 ISO1I811T electrical characteristics 1) not subject to production test, specified by design table 13 logical pins (rd , ds0/1, cs , d7:d0, sclk, sdo, sdi, sel) parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. input voltage high level v ih 0.7v vcc v vcc +0.3 v input voltage low level v il -0.3 0.3v vcc v input voltage hysteresis v ihys 100 mv output voltage high level v oh 0.75v vcc 1v vcc vi oh = 5ma output voltage low level v ol 00.25v vcc vi ol = 5ma table 14 parallel interface parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. input pull up resistance (rd , cs ) r pu 50 k ? read request frequency f rd 0.06 1) 1) minimum value to guarantee that the direct control mode is not entered, see also t rd and t direct 9 mhz repeated read access during cs = low read request period (1/f rd )t rd 110 15000 2) 2) after 15 s the interface may enter the direct control mode, see also t dimo ns cs setup time (falling edge of cs to falling edge of rd ) t css 55 ns cs disable time (minimum cs high time between two accesses) t csd 35 s d7:d0 output disable time t float 60 80 ns vcc = 3.3v vcc = 5.0v d0-7 output valid (by read) t valid 55 55 ns vcc = 3.3v vcc = 5.0v /rd low duration (by read) t rdlow 55 ns waiting time for cs =rd =0 until transparent mode is entered t direct 30 s ) 1) 3) 3) not subject to production test, specified by design table 15 serial interface parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. input pull up resistance ( c s )r pu 50 k ? input pull down resistance (sclk, sdi) r pd 50 k ?
ISO1I811T electrical characteristics preliminary data sheet 28 v1.0, 2011-03-18 serial clock frequency f sclk 9 10 mhz vcc = 3.3v vcc = 5.0v serial clock period (1/f sclk )t sclk 110 100 ns vcc = 3.3v vcc = 5.0v serial clock high period t sclkh 55 50 ns vcc = 3.3v vcc = 5.0v serial clock low period t sclkl 55 50 ns vcc = 3.3v vcc = 5.0v data setup time (r equired time sdi to rising edge of sclk) t su 5ns data hold time (rising edge of sclk to sdi) t hd 15 ns minimum cs hold time (rising edge of sclk to rising edge of cs ) t csh 40 ns minimum cs disable time (cs high time between two accesses) t csd 24 s ) 1) c s falling edge to sdo output valid time t cs_valid 50 ns /cs falling edge to first rising sclk edge t sclk_su 80 ns sclk falling edge to sdo output valid time t sclk_valid 80 70 ns vcc = 3.3v vcc = 5.0v minimum sdo output disable time t float 50 65 ns vcc = 3.3v vcc = 5.0v 1) valid for f scantyp = 100khz table 15 serial interface (cont?d) parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max.
preliminary data sheet 29 v1.0, 2011-03-18 ISO1I811T electrical characteristics
confidential ISO1I811T package outline preliminary data sheet 30 v1.0, 2011-03-18 , 6 package outline figure 6-1 package outline tssop-48 (tie bar not drawn in outline) notes 1. you can find all of our packages, sorts of packing an d others in our infineon internet page ?products?: http://www.infineon.com/products . 2. dimensions in mm.
published by infineon technologies ag www.infineon.com

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